Receiver

ABSTRACT

Receiver comprising an RF front end circuit for a selection and conversion of an RF input signal into a pair of quadrature IF (intermediate frequency) signals being supplied through in-phase and phase quadrature signal paths to signal inputs of quadrature phase detection means included in a (PLL) phase locked loop, an output of said quadrature phase detection means being coupled through a loop filter to a control input of a quadrature IF oscillator supplying a pair of quadrature IF oscillator signals to carrier inputs of said quadrature phase detection means. To suppress amplitude and phase mismatch deteriorating proper mirror cancellation said quadrature phase detection means is coupled to amplitude and phase error detection means for a detection of amplitude and phase errors in the output signal of said quadrature phase detection means and a quadrature frequency doubler is coupled between the quadrature local oscillator and carrier inputs of said amplitude and phase error detection means to supply respectively thereto in-phase and phase quadrature error detection carrier signals at twice the IF carrier frequency of said pair of quadrature IF signals, said amplitude and phase error detection means respectively providing amplitude and phase error signals through first and second low-pass filters to an amplitude correction circuit and a phase correction circuit preceding at least one of the inputs of said quadrature phase detection means for a negative feedback of said amplitude and phase errors.

[0001] The invention relates to a receiver comprising an RF front endcircuit for a selection and conversion of an RF input signal into a pairof quadrature signals being supplied through in-phase and phasequadrature signal paths to signal inputs of quadrature phase detectionmeans included in a (PLL) phase locked loop, an output of saidquadrature phase detection means being coupled through a loop filter toa control input of a quadrature IF oscillator supplying a pair ofquadrature IF oscillator signals through in-phase and phase quadratureIF carrier paths to carrier inputs of said quadrature phase detectionmeans. Such receiver is on itself known, e.g. from German Patent DE 3412 191.

[0002] Signal processing in receivers of this type generally amounts tothe following: the RF front end provides broadband selection andautomatic gain controlled amplification of a received RF frequency rangeand comprises a tuning stage for a conversion of a wanted RF inputsignal within said received RF frequency range to a predetermined fixedIF (intermediate frequency) using a tuning oscillator generating atuning oscillator signal at a frequency differing from the carrierfrequency of the wanted RF input signal by said fixed IF. In the knownreceiver, phase splitting is obtained by the use of quadrature mixers inthe tuning stage, providing the above pair of quadrature IF signals.Alternatively, phase splitting may be obtained by the use of resonanceamplifiers such as known from e.g. U.S. Pat. No. 5,220,686 in the RF orIF signal path. The quadrature IF signals are frequency demodulated inthe PLL to obtain the wanted baseband FM modulation signal, which isavailable at an output of the quadrature phase detection means to befurther processed for reproduction. The loop filter selects from anoutput signal of the quadrature phase detection means a control signalfor the IF oscillator varying with the phase differences between thequadrature IF oscillator signals on the one hand and the incomingquadrature IF signals on the other hand. This control signal providesfor a negative feed back of any such phase differences to the inputs ofthe quadrature phase detection means, resulting in the quadrature IFoscillator signals being phase synchronized with the incoming quadratureIF signals.

[0003] However, the frequency distribution of the RF transmissionsignals throughout the received RF frequency range gives rise tofrequency dispositions, in which a wanted RF signal finds an unwanted RFsignal located around a mirror frequency, i.e. at an RF carrierfrequency which in the receiver folds back in or close to the basebandmodulation frequency range of the wanted RF signal. Such frequencydisposition is depicted in the diagram of FIG. 1A, in which a wanted RFsignal W carrying a baseband modulation signal s is located around acarrier frequency f_(W), and the unwanted signal—hereinafter beingreferred to as mirror signal M—at a carrier frequencyf_(M)=f_(W)+2*f_(IF)+Δf, in which f_(IF) is the IF receiver frequencyand Δf as depicted being smaller than the frequency range of thebaseband modulation signal s.

[0004] In FIG. 1B the frequency disposition of the wanted and mirrorsignals W and M is depicted in the IF range after RF/IF conversion inthe tuning stage. The RF/IF conversion not only provides down conversionof the wanted RF signal W to a positive frequency f_(IF), but also foldsthe carrier frequency of the unwanted mirror signal M around the tuningoscillator frequency f_(TO) to a negative frequency f_(IF)+Δf, occurringwithin the frequency range of the useful baseband signal s of the wantedIF signal W.

[0005] The mirror signal M at said negative frequency f_(IF)+Δf can becancelled with an exact RF/IF phase quadrature signal processing. Inpractice, however, amplitude and/or phase errors due to e.g. parasiticeffects, tolerance spread and other sources of mismatch, cannot becompletely avoided and many efforts have been made to obtain mirror orimage rejection by measures such as precise balancing, accuratematching, narrow tolerances, and/or by the use of polyphase filters,such as known from e.g. the article “CMOS Mixers and Polyphase Filtersfor Large Image Rejection” by F. Behbahani et al., published in IEEEJournal of Solid-State Circuits, Volume 36, No. 6, June 2001, pages873-887. The effect of these known measures, however, is limited andresults in partly suppressed mirror signals, such as illustrated in FIG.1C with mirror signal M. Dependent on its frequency location andamplitude, such partly suppressed mirror signal may become noticeable asa strong deterioration of the wanted signal W.

[0006] Now, therefore, it is an object of the invention to provide aneffective mirror or image rejection which adds to the image rejectionobtained by the above known measures, and can be used independenttherefrom, and/or which allows to loosen the amplitude and phasematching requirements for image rejection in the known RF/IF quadraturesignal processing means.

[0007] This object is achieved in a receiver as described in the openingparagraph according to the invention, which is characterized by saidquadrature phase detection means being coupled to amplitude and phaseerror detection means for a detection of amplitude and phase errors inthe output signal of said quadrature phase detection means, a quadraturefrequency doubler being coupled between the quadrature IF oscillator andcarrier inputs of said amplitude and phase error detection means tosupply thereto respectively, in-phase and phase quadrature errordetection carrier signals at twice the frequency of said quadrature IFoscillator signals, said amplitude and phase error detection means beingcoupled respectively through first and second low-pass filters to anamplitude correction circuit and a phase correction circuit for anegative feedback of said amplitude and phase errors to said in-phaseand phase quadrature signal paths.

[0008] The invention is based on the recognition that demodulation of apair of quadrature IF signals which are mutually not precisely equal inamplitude and/or not precisely phase orthogonal, gives rise to a carriersignal E in baseband at 2*f_(IF) carrying the amplitude and phasemismatch or errors, as depicted in FIG. 1D. The larger the amplitude andphase errors, the stronger said 2*f_(IF) carrier signal E, and, asexplained above, also the stronger the mirror signal M. This means thatreduction of said 2*f_(IF) carrier signal E, hereinafter also beingreferred to as mismatch or error signal carrier, will result in asuppression of said mirror signal M.

[0009] By applying the invention, both amplitude and phase mismatch ofthe quadrature IF signals are being detected from said mismatch carrierE at 2*f_(IF) and negatively fed back from the output of said quadraturephase detection means to the in-phase and phase quadrature signal paths.As a result of this negative feed back, the mismatch carrier E isstrongly suppressed in both amplitude and phase and along therewith alsothe unwanted mirror signal M in the reproduced wanted basebandmodulation signal s. The invention restores the amplitude symmetry andorthogonal phase shift between the in-phase and phase quadrature IFsignals, hereinafter in short being referred to as quadrature symmetry,and therewith adds to any eventual mirror suppression obtained by theapplication of the above known measures. Apart from the unwanted mirrorsignal M and the mismatch carrier E at 2*f_(IF) the above demodulationof the pair of quadrature IF signals also causes a mirror signal M' tooccur at a positive baseband frequency 2*f_(IF)+Δf, which does notdepend on any quadrature symmetry mismatch. In view of its frequencydistance with regard to the useful baseband modulation signal s, thismirror signal M' can easily be suppressed.

[0010] Various forms of implementation of the abovementioned negativefeedback of said amplitude and phase errors to said in-phase and phasequadrature signal paths are possible. An indirect form of negativefeedback of quadrature symmetry errors is on itself known from U.S. Pat.No. 4,633,315.

[0011] An embodiment of a receiver according to the invention in whichthe quadrature symmetry of the RF or IF signals is restored directly ischaracterized by said amplitude and phase correction circuits beingincluded in at least one of the in-phase and phase quadrature signalpaths preceding the quadrature phase detection means.

[0012] An embodiment of a receiver according to the invention in whichthe quadrature symmetry of the IF signals is restored indirectly ischaracterized by said amplitude and phase correction circuits beingincluded in at least one of said in-phase and phase quadrature IFcarrier paths between the quadrature IF oscillator and the quadraturephase detection means.

[0013] An embodiment of a receiver according to the invention in whichthe quadrature symmetry of the RF signals is restored indirectly ischaracterized by the RF front end circuit comprising an RF tuningoscillator supplying a pair of quadrature RF oscillator signals throughin-phase and phase quadrature RF carrier paths to carrier inputs of aquadrature tuning stage, said amplitude and phase correction circuitsbeing included in at least one of said in-phase and phase quadrature RFcarrier paths preceding said quadrature tuning stage.

[0014] An embodiment of a receiver according to the invention in whichthe quadrature symmetry of the RF signals is restored directly ischaracterized by the RF front end circuit comprising a quadrature phasesplitter converting the RF input signal into a pair of quadrature RFsignals followed by said amplitude and phase correction circuitspreceding said quadrature tuning stage.

[0015] For a simple implementation, said amplitude correction circuitpreferably comprises a first multiplier included in at least one of saidin-phase and quadrature paths for an amplitude variation of the signalat said input with said amplitude error.

[0016] To balance out spurious response and DC offset from the amplitudecorrection circuit, an embodiment of a receiver according to theinvention is characterized by said amplitude correction circuitcomprising a differential stage following said first low pass filterconverting said amplitude error into a differential pair of first andsecond amplitude error signals and supplying the same to said first anda second multiplier, respectively, said first and second multipliersbeing included in said in-phase and phase quadrature paths.

[0017] For a simple implementation of the phase correction circuit, anembodiment of a receiver according to the invention is characterized byby said phase correction device comprising a third multiplier having asignal input coupled to one of said in-phase and quadrature paths and asignal output coupled to a first adder device, which is included in theother of said in-phase and quadrature paths for supplying thereto a partof the signal occurring at said one path to said other path varying withsaid phase error.

[0018] To balance out spurious response and DC offset from the phasecorrection circuit, an embodiment of a receiver according to theinvention is characterized by said phase correction circuit comprising adifferential stage following said second low pass filter converting saidphase error into a differential pair of first and second phase errorsignals and supplying the same to modulation signal inputs of said thirdand a fourth multiplier, respectively, said third and fourth multipliershaving inputs coupled to the phase quadrature and in-phase paths andhaving outputs coupled to said first and a second adder device, whichare included in said in-phase and phase quadrature paths, respectively.

[0019] To obtain a proper control signal for quadrature IF oscillator,crossing zero level at phase lock said quadrature phase detection meanspreferably comprises in-phase and phase quadrature phase detectors,signal inputs thereof being supplied with in-phase and phase quadratureIF signals of said pair of quadrature IF signals, carrier inputs thereofbeing respectively supplied with phase quadrature and in-phase IFoscillator signals of said pair of quadrature IF oscillator signals andin-phase and phase quadrature outputs thereof being coupled to inputs ofa subtracting stage, an output of said subtracting stage being coupledthrough a loop filter to a control input of said quadrature IFoscillator.

[0020] An embodiment of a receiver according to the invention using thebaseband FM modulation signal included in the output signal of thequadrature phase detection means is characterized by an output of saidsubtracting stage being coupled to a baseband FM modulation signalprocessor.

[0021] An embodiment of a receiver according to the invention allowingto eliminate mirror signals from a wanted baseband amplitude modulationsignal is characterized by quadrature amplitude demodulation means,comprising in-phase and phase quadrature synchronous amplitudedetectors, signal inputs thereof being supplied with said in-phase andphase quadrature IF signals, carrier inputs thereof being respectivelysupplied with said in-phase and phase quadrature IF oscillator signalsand in-phase and phase quadrature outputs thereof being coupled toinputs of an adding stage, an output of said adding stage being coupledthrough a loop filter to a baseband AM modulation signal processor.

[0022] These and further aspects and advantages of the invention will bediscussed more in detail hereinafter with reference to the disclosure ofpreferred embodiments, and in particular with reference to the appendedFigures, wherein

[0023]FIG. 1A is an amplitude (A)—frequency (f) diagram showing thefrequency disposition of a wanted RF signal carrying a basebandmodulation signal s, and its unwanted mirror signal within a received RFfrequency range;

[0024]FIG. 1B is an amplitude (A)—frequency (f) diagram showing thewanted signal and its unwanted mirror signal within the IF frequencyrange;

[0025]FIG. 1C is an amplitude (A)—frequency (f) diagram showing thewanted IF signal and its unwanted partly suppressed IF mirror signal;

[0026]FIG. 1D is an amplitude (A)—frequency (f) diagram showing thewanted IF signal, its unwanted partly suppressed IF mirror signal and amismatch carrier E at 2*f_(IF) in a baseband frequency range;

[0027]FIG. 2A shows a preferred embodiment of a receiver according tothe invention. In the Figures, identical parts are provided with thesame reference numbers;

[0028]FIG. 2B shows an alternative embodiment of a RF front end circuitfor use in a receiver according to the invention.

[0029]FIG. 2A shows a receiver according to the invention comprising anRF front end circuit 1 being supplied with an RF input frequency rangefrom antenna means ANT through an RF input RFI and includingsubsequently coupled to said RF input RFI, an RF input stage 2 for abroadband selection and automatic gain controlled amplification of saidRF input frequency range, a tuning stage 3 being provided with aquadrature pair of tuning mixers 3′ and 3″ supplied with a pair ofquadrature tuning oscillator signals provided by a quadrature tuningoscillator 4 for a conversion of a wanted RF signal within the RF inputfrequency range to a predetermined fixed IF (intermediate frequency) andsimultaneous quadrature phase splitting, resulting in a pair ofquadrature IF signals, the in-phase IF signal thereof being supplied toan in-phase signal path I, the phase quadrature IF signal thereof beingsupplied to a phase quadrature signal path Q, and an IF stage 5 for anarrowband channel selection and amplification of said pair ofquadrature IF signals. The IF stage 5 may include an IF polyphase filtersuch as known from the above cited article “CMOS Mixers and PolyphaseFilters for Large Image Rejection” by F. Behbahani et al., published inIEEE Journal of Solid-State Circuits, Volume 36, No. 6, June 2001, pages873-887. The frequency of said pair of quadrature tuning oscillatorsignals differs from the carrier frequency of the wanted RF input signalby said fixed IF. The pair of quadrature IF signals is being suppliedfrom outputs of said IF stage 5 through said in-phase and phasequadrature signal paths I and Q to signal inputs of quadrature phasedetection means 6-8, comprising in-phase and phase quadrature phasedetectors 6 and 7 respectively, carrier inputs thereof beingrespectively supplied with phase quadrature and in-phase IF oscillatorsignals of a pair of quadrature IF oscillator signals and in-phase andphase quadrature outputs thereof being coupled to inputs of asubtracting stage 8, an output of said subtracting stage 8 being coupledthrough a loop filter 9 to a control input of a quadrature IF oscillator10. The quadrature phase detection means 6-8 together with the loopfilter 9 and the quadrature IF oscillator 10 form a phase locked loop,in which phase differences between the pair of quadrature IF signals onthe one hand and the pair of quadrature IF oscillator signals on theother hand are being measured by the quadrature phase detection means6-8 and negatively fed back from the output of the subtracting stage 8through the control signal of the quadrature IF oscillator 10 to saidpair of quadrature IF oscillator signals. This results in a suppressionof said phase differences, which is at maximum in the in-lock state ofthe PLL, in which the pair of quadrature IF oscillator signals is fullyphase synchronized with the incoming pair of quadrature IF signals. Inthis in-lock state of the PLL the output signal of the quadrature phasedetection means 6-8 provides the baseband FM modulation signal, which issupplied to a baseband FM modulation signal processor 11 followed by aloudspeaker device 12 for reproduction of said baseband FM modulationsignal.

[0030] The receiver described sofar corresponds to the above knownreceiver and needs no further amplification for a proper understandingof the invention.

[0031] As explained above with reference to FIGS. 1A-1D, mismatch in thequadrature RF/IF signal processing, causing the quadrature IF signals tomutually deviate from quadrature symmetry, i.e. to mutually differ inamplitude and/or to mutually differ in phase from a 90° phase shift,deteriorate proper cancellation of mirror signals at negativefrequencies, such as the mirror signal M shown in FIGS. 1A-1D. Accordingto the invention, mirror cancellation is obtained by an accuratedetection and suppression of said amplitude and phase mismatch as willnow be explained in more detail.

[0032] Suppose the amplitude mismatch or amplitude error of the pair ofin-phase and phase quadrature IF signals IFI and IFQ in the in-phase andphase quadrature signal paths I and Q, respectively, is δA and the phasemismatch or phase error δΦ is zero. Then with ω_(IF)=2πf_(IF), IFI andIFQ are defined by:

IFI=(1+δA)*cos ω_(IF)t

IFQ=sinω_(IF)t

[0033] With VCOI and VCOQ being the in-phase and phase quadrature IFoscillator signals of the pair of quadrature IF oscillator signals,without amplitude error 6A and with phase error φ with respect to IFIand IFQ, these signals can be written as:

VCOI=cos(ω_(IF) t+φ)

VCOQ=sin(ω_(IF) t+φ)

[0034] The quadrature phase detection means 6-8 provides at its output aphase detector output signal PDOUT, defined by IFI*VCOQ−IFQ*VCOI withamplitude error δA and phase error φ.

PDOUT=IFI*VCOQ−IFQ*VCOI

PDOUT=(1+δA)*cosω_(IF) t*sin(ω _(IF) t+φ)−sinω_(IF) t*cos(ω_(IF) t+φ)

PDOUT=cosω_(IF) t*sin(ω_(IF) t+φ)−sinω_(IF) t*cos(ω_(IF)t+φ)+δA*cosω_(IF) t*sin(ω_(IF) t+φ)

PDOUT=sin(φ)+δA*cosω_(IF) t*sin(ω_(IF) t+φ)

[0035] In the in-lock state of the PLL 6-10, the phase error φ is fullysuppressed (φ−>0) as explained above, resulting in:

PDOUT=sin(0)+δA/2*2*cosω_(IF) t*sin(ω_(IF) t)

PDOUT=δA/2*sin(2*ω_(IF)t)

[0036] This means that in the in-lock state of the PLL 6-10, theamplitude of the unwanted mirror signal M is present at the output ofthe quadrature phase detection means 6-8 as an amplitude modulatedsignal δA/2*sin(2*ω_(IF)t) at a carrier of two times the intermediatefrequency f_(IF). With a synchronous amplitude detector using anin-phase (i.e. sinus-phase) detection carrier at the frequency 2*f_(IF)and a low pass filter the amplitude error δA can be detected and reducedin a loop with negative feedback as will be described in further detailhereinafter.

[0037] Suppose the pair of in-phase and phase quadrature IF signals IFIand IFQ in the in-phase and phase quadrature signal paths I and Q,respectively, having a mutual phase deviation differing from 90° by aphase error ox without amplitude error. Then:

IFI=cosω_(IF) t+δΦ*sin(ω_(IF) t)

IFQ=sinω_(IF)t

[0038] In the in-lock state of the PLL, i.e. with phase error (p beingzero and without amplitude error δA and phase error δΦ, the in-phase andphase quadrature IF oscillator signals can be written as:

VCOI=cosω_(IF)t

VCOQ=sinω_(IF)t

[0039] The quadrature phase detection means 6-8 provides at its output aphase detector output signal PDOUT, defined by IFI*VCOQ−IFQ*VCOI withphase error δΦ only.

PDOUT=IFI*VCOQ−IFQ*VCOI

PDOUT=(cosω_(IF) t+δΦ*sinω_(IF) t)*sinω_(IF) t−sinω_(IF) t*cosω_(IF) t

PDOUT=cosω_(IF) t*sinω_(IF) t−sinω_(IF) t*cosω_(IF) t+δΦ*sinω_(IF)t*sinω_(IF) t

PDOUT=0+δΦ*sinω_(IF) t*sinω_(IF) t

PDOUT=0+δΦ/2*(1−cos(2*ω_(IF) t))

PDOUT=δΦ/2−δΦ/2*cos(2ω_(IF) t)

[0040] This means that in the in-lock state of the PLL 6-10, anamplitude error δΦ is present at the output of the phase detector as anadditional phase error and at the same time as amplitude modulatedsignal—δΦ/2*cos(2*ω_(IF)t) at a carrier of two times the intermediatefrequency f_(IF), also being referred to as mismatch or error signalcarrier E. With a synchronous amplitude detector using a quadraturephase (i.e. cosinus-phase) detection carrier at the frequency 2*f_(IF)and a low pass filter the phase error δΦ can be detected and reduced ina loop with negative feedback as will be described in further detailhereinafter.

[0041] According to the invention, the output of said quadrature phasedetection means 6-8 is coupled to amplitude and phase error detectionmeans 13 and 14 being constituted by synchronous amplitude and phasedetectors for a detection of amplitude and phase errors δA and δΦ in theoutput signal of said quadrature phase detection means 6-8 caused byamplitude and/or phase mismatches in the quadrature receiver signalprocessing due to e.g. parasitic effects, tolerance spread and othersources of mismatch. A quadrature frequency doubler 15 is coupledbetween the quadrature IF oscillator 10 and carrier inputs of saidamplitude and phase error detection means 13 and 14 to supplyrespectively thereto in-phase and phase quadrature error detectioncarrier signals at twice said IF carrier frequency, i.e. at 2*f_(IF),said amplitude and phase error detection means 13 and 14 providingamplitude and phase error signals δA and δΦ through first and secondlow-pass filters 15 and 16 to an amplitude correction circuit 17-19 anda phase correction circuit 20-24 preceding the signal inputs of saidquadrature phase detection means 6-8 for a negative feedback of saidamplitude and phase errors δA and δΦ to said in-phase and phasequadrature signal paths I and Q. Due to this negative feed back, anyoccurrence of amplitude and phase errors δA and δΦ in the output signalof the quadrature phase detection means 6-8 is followed by a correctionof these errors in the signals of the in-phase and phase quadraturesignal paths I and Q, resulting in a suppression of the initialamplitude and phase errors and therewith in a suppression of thebaseband mirror signal M, in the given example of FIG. 1D occurring at abaseband frequency Δf.

[0042] The frequency doubler 15 may be constituted by a known frequencydoubler such as disclosed in e.g. U.S. Pat. No. 5,389,886.

[0043] The amplitude correction circuit 17-19 comprises a differentialstage 17 following said first low pass filter 15 converting saidamplitude error signal δA into a differential pair of first and secondamplitude error signals +0.5δA and −0.5δA and supplying the same tofirst and second multipliers 18 and 19, respectively, said first andsecond multipliers 18 and 19 being included in said in-phase and phasequadrature signal paths I and Q preceding the signal inputs ofquadrature phase detection means 6-8.

[0044] The phase correction circuit 20-24 comprises a differential stage20 following said second low pass filter 16 converting said phase errorsignal δΦ into a differential pair of first and second phase errorsignals +0,5δΦ and −0.5δΦ and supplying the same to modulation signalinputs of third and fourth multipliers 21 and 22, respectively, saidthird and a fourth multipliers 21 and 22 having inputs coupled to thein-phase and phase quadrature signal paths I and Q and having outputscoupled through said first and a second adder device 23 and 24 to thephase quadrature and in-phase signal paths Q and I, respectively,preceding the signal inputs of quadrature phase detection means 6-8.

[0045] For the reception of AM signals, the receiver is provided withquadrature amplitude demodulation means 25-27, comprising in-phase andphase quadrature synchronous amplitude detectors 25 and 26, signalinputs thereof being supplied with the above in-phase and phasequadrature IF signals IFI and IFQ, carrier inputs thereof beingrespectively supplied with the in-phase and phase quadrature IFoscillator signals VCOI and VCOQ and in-phase and phase quadratureoutputs thereof being coupled to inputs of an adding stage 27, an outputof said adding stage 27 being coupled through a baseband AM modulationsignal processor 28 to a loudspeaker device 29.

[0046]FIG. 2A shows quadrature phase splitting obtained in the RF inputstage 2 by the use of resonance amplifiers such as known from e.g. U.S.Pat. No. 5,220,686, converting the single phase RF input signal into apair of quadrature RF signals being supplied to in-phase and phasequadrature RF signal paths. In this alternative embodiment of the RFfront end circuit 1, the amplitude and phase correction means 18, 19 and21-24, respectively, may be included in said in-phase and phasequadrature RF signal paths preceding the quadrature tuning stage 3,whereas only a single phase oscillator signal is needed for an RF to IFconversion of said pair of quadrature RF signals.

[0047] The invention is not limited to the embodiments explicitlydisclosed. It may well be possible without leaving the scope and spiritof the invention, to dispense with the differential stages 17 and 20e.g. by correcting for both phase and amplitude mismatch in either thein-phase signal path I only, or in the phase quadrature signal path Qonly, or to carry out such corrective measure indirectly on the signalsof the in-phase and phase quadrature IF signal paths I and Q through aquadrature symmetry correction of the in-phase and phase quadrature IFoscillator signals VCOI and VCOQ of the local IF oscillator 10 precedingthe carrier inputs of the quadrature phase detection means 6-8, such ason itself known from U.S. Pat. No. 4,633,315. Such indirect correctionof the quadrature symmetry of the signals in the in-phase and phasequadrature RF signal paths I and Q may well be possible by a correctionof the in-phase and phase quadrature tuner oscillator signals of thetuning oscillator 4 preceding the carrier inputs of the quadrature pairof tuning mixers of the tuning stage 3.

[0048] The invention is embodied in each new characteristic and eachcombination of characteristics. Any reference signs do not limit thescope of the claims. The word “comprising” does not exclude the presenceof other elements than those listed in a claim. Use of the word “a” or“an” preceding an element does not exclude the presence of a pluralityof such elements.

1. A receiver comprising: an RF front end circuit, quadrature phasedetectors, a quadrature IF oscillator, an amplitude error detector, aphase error detector, a quadrature frequency doubler, an amplitudecorrection circuit, and a phase correction circuit, wherein the RF frontend circuit is configured for a selection and conversion of an RF inputsignal into a pair of quadrature signals that are supplied throughin-phase and phase quadrature signal paths to signal inputs of thequadrature phase detectors, which are included in a (PLL) phase lockedloop, an output of the quadrature phase detectors are coupled through aloop filter to a control input of the quadrature IF oscillator, thequadrature IF oscillator is configured to supply a pair of quadrature IFoscillator signals through in-phase and phase quadrature IF carrierpaths to carrier inputs of the quadrature phase detectors, thequadrature phase detectors are coupled to the amplitude and phase errordetectors for a detection of amplitude and phase errors in the outputsignal of the quadrature phase detectors, the quadrature frequencydoubler is coupled between the quadrature IF oscillator and carrierinputs of the amplitude and phase error detectors to supply theretorespectively, in-phase and phase quadrature error detection carriersignals at twice the frequency of the quadrature IF oscillator signals,and the amplitude and phase error detectors are coupled respectivelythrough first and second low-pass filters to an amplitude correctioncircuit and the a phase correction circuit for a negative feedback ofthe amplitude and phase errors to the in-phase and phase quadraturesignal paths.
 2. A receiver as claimed in claim 1, wherein the amplitudeand phase correction circuits are included in at least one of thein-phase and phase quadrature signal paths preceding the quadraturephase detectors.
 3. A receiver as claimed in claim 1, wherein theamplitude and phase correction circuits are included in at least one ofthe in-phase and phase quadrature IF carrier paths between thequadrature IF oscillator and the quadrature phase detectors.
 4. Areceiver as claimed in claim 1, wherein the RF front end circuitcomprises an RF tuning oscillator that is configured to supply a pair ofquadrature RF oscillator signals through in-phase and phase quadratureRF carrier paths to carrier inputs of a quadrature tuning stage, and theamplitude and phase correction circuits are included in at least one ofthe in-phase and phase quadrature RF carrier paths preceding thequadrature tuning stage.
 5. A receiver as claimed in claim 1, whereinthe RF front end circuit comprises a quadrature phase splitter that isconfigured to convert the RF input signal into a pair of quadrature RFsignals followed by the amplitude and phase correction circuitspreceding the quadrature tuning stage.
 6. A receiver as claimed in claim1, wherein the amplitude correction circuit comprises a first multiplierincluded in at least one of the in-phase and quadrature paths for anamplitude variation of the signal at the input with the amplitude error.7. A receiver as claimed in claim 6, wherein the amplitude correctioncircuit comprises a differential stage following the first low passfilter converting the amplitude error into a differential pair of firstand second amplitude error signals and supplying the same to the firstand a second multiplier, respectively, and the first and secondmultipliers are included in the in-phase and phase quadrature paths. 8.A receiver as claimed in claim 7, wherein the phase correction devicecomprises a third multiplier having a signal input coupled to one of thein-phase and quadrature paths and a signal output coupled to a firstadder device, and the first adder device is included in the other of thein-phase and quadrature paths for supplying thereto a part of the signaloccurring at the one path to the other path varying with the phaseerror.
 9. A receiver as claimed in claim 8, wherein the phase correctioncircuit comprises a differential stage following the second low passfilter that is configured to convert the phase error into a differentialpair of first and second phase error signals and to supply the same tomodulation signal inputs of the third and a fourth multiplier,respectively, the third and fourth multipliers having inputs coupled tothe phase quadrature and in-phase paths and having outputs coupled tothe first and a second adder device, which are included in the in-phaseand phase quadrature paths, respectively.
 10. A receiver as claimed inclaim 1, wherein the quadrature phase detectors comprise in-phase andphase quadrature phase detectors, signal inputs thereof being suppliedwith in-phase and phase quadrature IF signals of the pair of quadratureIF signals, carrier inputs thereof being respectively supplied withphase quadrature and in-phase IF oscillator signals of the pair ofquadrature IF oscillator signals and in-phase and phase quadratureoutputs thereof being coupled to inputs of a subtracting stage, anoutput of the subtracting stage being coupled through a loop filter to acontrol input of the quadrature IF oscillator.
 11. A receiver as claimedin claim 10, wherein the output of the subtracting stage is coupled to abaseband FM modulation signal processor.
 12. A receiver as claimed inclaim 1, further including a quadrature amplitude demodulator comprisingin-phase and phase quadrature synchronous amplitude detectors, signalinputs thereof being supplied with the in-phase and phase quadrature IFsignals, carrier inputs thereof being respectively supplied with thein-phase and phase quadrature IF oscillator signals and in-phase andphase quadrature outputs thereof being coupled to inputs of an addingstage, an output of the adding stage being coupled through a loop filterto a baseband AM modulation signal processor.
 13. A receiver as claimedin claim 3, wherein the amplitude correction circuit comprises a firstmultiplier included in at least one of the in-phase and quadrature pathsfor an amplitude variation of the signal at the input with the amplitudeerror.
 14. A receiver as claimed in claim 4, wherein the amplitudecorrection circuit comprises a first multiplier included in at least oneof the in-phase and quadrature paths for an amplitude variation of thesignal at the input with the amplitude error.
 15. A receiver as claimedin claim 5, wherein the amplitude correction circuit comprises a firstmultiplier included in at least one of the in-phase and quadrature pathsfor an amplitude variation of the signal at the input with the amplitudeerror.
 16. A receiver as claimed in claim 13, wherein the amplitudecorrection circuit comprises a differential stage following the firstlow pass filter converting the amplitude error into a differential pairof first and second amplitude error signals and supplying the same tothe first and a second multiplier, respectively, and the first andsecond multipliers are included in the in-phase and phase quadraturepaths.
 17. A receiver as claimed in claim 14, wherein the amplitudecorrection circuit comprises a differential stage following the firstlow pass filter converting the amplitude error into a differential pairof first and second amplitude error signals and supplying the same tothe first and a second multiplier, respectively, and the first andsecond multipliers are included in the in-phase and phase quadraturepaths.
 18. A receiver as claimed in claim 15, wherein the amplitudecorrection circuit comprises a differential stage following the firstlow pass filter converting the amplitude error into a differential pairof first and second amplitude error signals and supplying the same tothe first and a second multiplier, respectively, and the first andsecond multipliers are included in the in-phase and phase quadraturepaths.
 19. A receiver as claimed in claim 16, wherein the phasecorrection device comprises a third multiplier having a signal inputcoupled to one of the in-phase and quadrature paths and a signal outputcoupled to a first adder device, and the first adder device is includedin the other of the in-phase and quadrature paths for supplying theretoa part of the signal occurring at the one path to the other path varyingwith the phase error.
 20. A receiver as claimed in claim 17, wherein thephase correction device comprises a third multiplier having a signalinput coupled to one of the in-phase and quadrature paths and a signaloutput coupled to a first adder device, and the first adder device isincluded in the other of the in-phase and quadrature paths for supplyingthereto a part of the signal occurring at the one path to the other pathvarying with the phase error.
 21. A receiver as claimed in claim 18,wherein the phase correction device comprises a third multiplier havinga signal input coupled to one of the in-phase and quadrature paths and asignal output coupled to a first adder device, and the first adderdevice is included in the other of the in-phase and quadrature paths forsupplying thereto a part of the signal occurring at the one path to theother path varying with the phase error.
 22. A receiver as claimed inclaim 4, wherein the quadrature phase detectors comprise in-phase andphase quadrature phase detectors, signal inputs thereof being suppliedwith in-phase and phase quadrature IF signals of the pair of quadratureIF signals, carrier inputs thereof being respectively supplied withphase quadrature and in-phase IF oscillator signals of the pair ofquadrature IF oscillator signals and in-phase and phase quadratureoutputs thereof being coupled to inputs of a subtracting stage, anoutput of the subtracting stage being coupled through a loop filter to acontrol input of the quadrature IF oscillator.
 23. A receiver as claimedin claim 5, wherein the quadrature phase detectors comprise in-phase andphase quadrature phase detectors, signal inputs thereof being suppliedwith in-phase and phase quadrature IF signals of the pair of quadratureIF signals, carrier inputs thereof being respectively supplied withphase quadrature and in-phase IF oscillator signals of the pair ofquadrature IF oscillator signals and in-phase and phase quadratureoutputs thereof being coupled to inputs of a subtracting stage, anoutput of the subtracting stage being coupled through a loop filter to acontrol input of the quadrature IF oscillator.
 24. A receiver as claimedin claim 7, wherein the quadrature phase detectors comprise in-phase andphase quadrature phase detectors, signal inputs thereof being suppliedwith in-phase and phase quadrature IF signals of the pair of quadratureIF signals, carrier inputs thereof being respectively supplied withphase quadrature and in-phase IF oscillator signals of the pair ofquadrature IF oscillator signals and in-phase and phase quadratureoutputs thereof being coupled to inputs of a subtracting stage, anoutput of the subtracting stage being coupled through a loop filter to acontrol input of the quadrature IF oscillator.
 25. A receiver as claimedin claim 9, wherein the quadrature phase detectors comprise in-phase andphase quadrature phase detectors, signal inputs thereof being suppliedwith in-phase and phase quadrature IF signals of the pair of quadratureIF signals, carrier inputs thereof being respectively supplied withphase quadrature and in-phase IF oscillator signals of the pair ofquadrature IF oscillator signals and in-phase and phase quadratureoutputs thereof being coupled to inputs of a subtracting stage, anoutput of the subtracting stage being coupled through a loop filter to acontrol input of the quadrature IF oscillator.
 26. A receiver as claimedin claim 25, wherein the output of the subtracting stage is coupled to abaseband FM modulation signal processor.
 27. A receiver as claimed inclaim 26, further including a quadrature amplitude demodulatorcomprising in-phase and phase quadrature synchronous amplitudedetectors, signal inputs thereof being supplied with the in-phase andphase quadrature IF signals, carrier inputs thereof being respectivelysupplied with the in-phase and phase quadrature IF oscillator signalsand in-phase and phase quadrature outputs thereof being coupled toinputs of an adding stage, an output of the adding stage being coupledthrough a loop filter to a baseband AM modulation signal processor.